Software Defined Radio / SDR

Siru Innovations - Software Defined Radio / SDR

What is SDR?

Software Defined Radios (SDR) will make traditional analog radio technology obsolete as SDR replaces many of the analog sections with software and enables unseen functionalities such as dynamic spectrum management, high throughput data links, and altogether a new level of intelligence in radio behavior.

Our SDR concept

As traditional analog radios aren’t capable of meeting modern requirements for performance, adaptivity, and hardware simplicity, we combined our different areas of expertise and created our own software defined radio concept. Our SDR20 is living proof of our SDR concept, our waveform development platform that we designed mainly for our own purposes, but has also proven to be a great tool as a base for hardware and firmware development for our customers.

We provide everything from full devices and systems to any part of the process you need help with.

Not just talk... a proof of concept!

SDR20 as an example includes Siru expertise in these areas:

  • Schematics and circuit board design
  • RF design
  • FPGA SoC hardware
  • User experience design
  • Hardware design


Previous experience in designing FPGA hardware, including power supplies, memory routings, building the operating system environment, basically everything needed to bring the FPGA alive, made the FPGA design just one more task in the SDR20 project.

We selected the 896-pin FPGA SoC chip, which meant that the circuit board needed 14 PCB layers. In such a design, multiple factors had to be considered, such as the coupling and isolation of the digital I/O lines, the circulating currents in the PCB, thermal management, and obviously smart mechanical layout.

The radio sections include low-noise high-gain amplifiers, radio frequency mixers, phase-linear filters, and switches. The whole system is designed to be coherent and can handle frequencies of up to 3 GHz. Our scope extends beyond the hardware and software, with the design of antennas, pre-amplifiers and so forth.

As we wanted a mobile low-power device, multiple factors needed to be taken into account, such as the casing and designing low-noise switching power supplies for low power consumption. Thanks to our in-house electronics and hardware R&D team, this project was fun and everything went smoothly.

Firmware and software

Our target was to receive and transmit 200 MHz of bandwidth in real time with high dynamic range on a frequency range from 200 kHz to 2.3 GHz. To achieve this challenge, very powerful, high-throughput, and time-critical signal processing was needed. Using our HLS (High-Level Synthesis) flow, focus was kept on the high level code development instead of wasting time on low level (register-transfer level) development. This enabled high-throughput and time-critical design. With a DSP and GPU on the same FPGA chip, the SDR20 is capable of drawing 200 MHz of real time bandwidth on the built-in touchscreen display.

All the signal processing, such as filters, FFT, modulators, demodulators, and so forth, is done within the FPGA, whereas the operating system running in the ARM processor handles the graphical user interface and controls the DSP (digital signal processing) flow and its parameters. We wanted a responsive and stunning user interface, so we developed a custom graphics processor that runs on the FPGA and interfaces directly with the DSP flow. Thanks to our GPU, now the ARM processing power can be used for the user interface.

As an example of the FPGA processing power, we produced an 8-channel VHF receiver with real-time independent DSP for every channel and with 6.4 Gbps data stream output over 10G Ethernet.


We have a dedicated waveform team for solving the challenges of modern spectral efficiency requirements. To mention a few implementations, SCFDM and OFDM waveform based modems are good examples of that we have produced as high-performance FPGA designs. As FPGA throughput doesn’t decrease with simultaneous parallel processes, beamforming is another perfect example of our implementations that benefits greatly from FPGA technology. These kinds of tasks are simple to produce with our HLS flow.